Electrostatic discharges occur naturally, e.g. by walking on a rug, and, although often have little energy, high voltages may occur. As it happens IC's are very susceptible to harm simply by voltage levels alone. For example, dielectric layers and/or other such isolation barriers may be damaged or destroyed, by the voltage alone. Moreover, voltage levels of a few volts above typical Vcc levels may harm modern IC's. There is a need to have ESD devices built onto IC chips that reliably trigger at fairly low levels.
There have been many suggestions of ways to lower the ESD triggering voltages. One such suggestion is found in U.S. Pat. No. 5,870,268 to Lin et al. This patent teaches generating, in response to an ESD event, a current spike that drives up the voltage of the p-well surrounding the ESD device. The higher P-well voltage lowers the trigger voltage of the ESD NMOS device down to the 12 volt level or so. This approach requires added circuitry, however.
Another patent, U.S. Pat. No. 5,932,914 discloses another approach using N-wells and an N type buried diffusion layer (NBL). The patent teaches forming, within the N type material envelope, an NPN protection transistor, and an NMOSFET protection device separated by a resistor. The patent claims the combination provides an improved ESD protection mechanism. The NBL participates in the formation of the NPN and the NMOS, but there is no disclosure of lowering and/or improving trigger levels. However, this N type material completely envelops the P-well carrying the ESD device and, thus, occupies more IC surface area than the ESD device itself would occupy.
There still is a need for a simple IC structure that provides a low ESD trigger level reliably without extensive overhead circuitry and with an efficient use of IC space.